Circuit Design Techniques for Multimedia Wireline Communications (Invited Paper)

This paper presents several circuit design techniques for multimedia wireline interfaces. A 7.5 Gb/s transceiver with pre-emphasis and bandwidth (BW)-shifting techniques are introduced. By applying dynamic calibration technique for pre-emphasis, the measured transmitter eye-opening is improved by 24 %. BW shifting clock generator achieves the jitter reduction of 43 %. In addition, a wide input range comparator for 11.2 Gb/s low-voltage-differential-swing (LVDS) multi-channel receiver is also introduced. The comparator achieves 81.9 % of the received data RMS jitter reduction for the LVDS receiver.