Noise-immune Design of Schmitt Trigger Logic Gate using DTMOS for Sub-threshold Circuits

被引：0

作者：

Kim, KyungSoo ^{[1
]}

Nah, Wansoo ^{[1
]}

Kim, So Young ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Dept Semicond Display Engn, IC Design & Solut Lab, Suwon, South Korea

来源：

2013 9TH INTERNATIONAL WORKSHOP ON ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2013) | 2013年

关键词：

Schmitt Trigger; hysteresis; DTMOS; VTMOS; noise immunity; EMI; EMC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents several Schmitt trigger logic gates with enhanced noise immunity using variable threshold voltage technique for sub-threshold voltage operation. The proposed logic gates are based on buffer design using dynamic threshold voltage MOS (DTMOS) for low power operation (V-DD=0.4V). Our solution dramatically improves noise immunity of logic gates with much less switching power consumption and significant area reduction compared with CMOS Schmitt triggers at the expense of slight increase in delay. The proposed noise immune gate design scheme is verified with an example digital circuit.

引用

页码：83 / 88

页数：6

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