Simulation of ESD Thermal Failures and Protection Strategies on System Level

被引:8
作者
Scheier, Stanislav [1 ]
zur Nieden, Friedrich [1 ]
Arndt, Bastian [2 ]
Frei, Stephan [1 ]
机构
[1] TU Dortmund Univ, On Board Syst Lab, D-44227 Dortmund, Germany
[2] AVL Trimer GmbH, D-93059 Regensburg, Germany
关键词
Electrostatic discharge (ESD); overcurrent destruction/failure; overvoltage destruction/failure; safe operating area (SOA); system-level ESD; thermal destruction/failure criterion; DEVICES;
D O I
10.1109/TEMC.2015.2442623
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, approaches for the modeling and simulation of thermal destruction of ICs due to ESD are discussed from a system point of view. Considered systems consist of ESD generator, PCB, protection element, and IC. A direct connection between the ESD generator and the system is always assumed. For the modeling of an IC ESD destruction, the electric behavior model of an IC pin to ground or supply is extended with a thermal destruction model. The thermal model consists mainly of a thermal resistance and a thermal capacitance. When structure temperature reaches a threshold, a failure is assumed. All needed model parameters can be found with a set of measurements and tests. No internal knowledge of the IC or protection element structures is required. The methodology was applied to several ICs, protection elements, and system structures with emphasis on automotive electronics. All needed component model parameters were generated from measurements. Models and parameter measurements are described. Results from the system simulation were compared to system test results with hardware. In most cases, the simulation could predict well the destruction behavior of a system. Thermal failure and safe operating area prediction quality are compared. The described simulation method helps with selection of protection strategies and optimization of system ESD robustness.
引用
收藏
页码:1309 / 1319
页数:11
相关论文
共 34 条
[1]  
Amerasekera E.A., 2002, ESD in Silicon Integrated Circuits, V2nd
[2]  
[Anonymous], 2008, IEC 61000-4-2, V2nd
[3]  
[Anonymous], 2010, 3 IND COUNC ESD TARG
[4]  
[Anonymous], 106052008 ISO
[5]  
[Anonymous], 2014, MICR IMP CALC
[6]  
[Anonymous], 2013, FAT SCHRIFT
[7]  
[Anonymous], 2014, TLP VF TLP TEST SYST
[8]  
[Anonymous], 10761 IEEE
[9]  
Baumgartner H., 1997, ESD ELEKTROSTATISCHE
[10]  
Bertonnaud S, 2012, ELECTR OVER ELECTRO