A 52GHz Millimeter-Wave PLL Synthesizer for 60GHz WPAN Radio

被引：0

作者：

Lee, Ja-Yol ^{[1
]}

Kim, Haecheon ^{[1
]}

Yu, Hyun-Kyu ^{[1
]}

机构：

[1] ETRI, SoC R&D Grp, Digital RF SoC Design Team, Taejon, South Korea

来源：

2008 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC) | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present the design of 52-GHz frequency synthesizer for 60GHz WPAN application. The PLL consists of 26GHz PILL and 52GHz frequency doubler, generating two channels of output carriers with 2.08GHz step by using high-speed four-modulus divider. The proposed PLL represents phase noise of - 89dBc/Hz from 26.2GHz carrier and - 81dBc/Hz from 52.4GHz carrier, at 1MHz offset, respectively. Also, its integrated RMS phase noise from 1MHz to 100MHz is measured as 7.42 degrees Output frequency tuning range from the PLL is 50 to 53-GHz. The synthesizer including frequency doubler consumes 160mA at 2.5V supply voltage and occupies 1.2 x 1.0 mm(2) chip area.

引用

页码：155 / 158

页数：4

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