Design advantages of run-time reconfiguration

FPGAs have been sucessfully used to accelerate a wide variety of applications on a large number of systems. The FPGA devices in these systems are typically configured once by the application and seldom perform any sort of reconfiguration during execution. With the advent of new device architectures and new software tools, the interest in Run- Time Reconfiguration or RTR has increased. As with previous efforts, the focus of RTR has primarily been either in purely theoretical work or in demonstrating performance improvements over software-based solutions. In this paper we explore some of the more practical design issues surrounding RTR systems, and evaluate the advantages of RTR in terms of savings in hardware and software complexity. Preliminary results indicate that RTR can dramatically reduce the amount of FPGA logic and software support necessary for even simple coprocessing applications.