A Low-Cost Fault-Tolerant Approach for Hardware Implementation of Artificial Neural Networks

被引：12

作者：

Ahmadi, A. ^{[1
]}

Sargolzaie, M. H. ^{[1
]}

Fakhraie, S. M. ^{[1
]}

Lucas, C. ^{[1
]}

Vakili, Sh. ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Silicon Intelligence & VLSI Signal Proc Lab, Tehran, Iran

来源：

2009 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING AND TECHNOLOGY, VOL II, PROCEEDINGS | 2009年

关键词：

Artificial Neural Networks; fault-tolerant; spare neuron;

D O I：

10.1109/ICCET.2009.204

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Artificial Neural Networks (ANN's) are widely used in computational and industrial applications. As technology is developed the scale of hardware is progressively becoming smaller and the number of faults is increasing. Therefore, fault-tolerant methods are necessary especially for ANNs used in critical applications. In this work, we propose a new method for fault-tolerant implementation of neural networks. In hidden and output layers, we add a spare neuron and one of hidden and output neurons is tested by each input pattern. Our technique detects and corrects any single fault in the network. We achieve complete fault tolerance for single faults with at most 40 % area overhead.

引用

页码：93 / 97

页数：5

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