A Low Power SHA-less Pipelined ADC used in DVB-S2

被引：0

作者：

Zhang, Zhang ^{[1
]}

Zeng, Xiaoyang ^{[1
]}

Li, Jian ^{[1
]}

Xie, Lei ^{[1
]}

Guo, Yawei ^{[2
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

[2] Comlent Technol Inc, Shanghai 201203, Peoples R China

来源：

2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 8-b 125MS/s pipelined Analog-to-Digital Converter (ADC) used in DVB-S2 is presented in this paper. Based on reviewing low-power design techniques of high speed ADCs, several technologies are used in the design including the SHA-less architecture to reduce the power dissipation significantly. Detailed analysis is given about the relationship between the closed loop bandwidth (BWclose) and the current of operational amplifier (OPAMP) used in Multiply Digital-to-Analog Converter (MDAC) to get the lowest power dissipation which can satisfy the ADC. The ADC is realized in SMIC 0.18um 1P6M CMOS process and according to the simulation results, the SNDR is 48dB with the power of 23.5mW.

引用

页码：1905 / +

页数：2

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