Digital lock in amplifier:: study, design and development with a digital signal processor

被引：49
作者：
Gaspar, J
Chen, SF
Gordillo, A
Hepp, M
Ferreyra, P
Marqués, C
机构：
[1] Natl Univ Cordoba, Fac Matemat Astron & Fis, RA-5000 Cordoba, Argentina
[2] Univ Nacl Cordoba, Fac Ciencias Exactas Fis & Nat, RA-5000 Cordoba, Argentina
来源：
MICROPROCESSORS AND MICROSYSTEMS | 2004年 / 28卷 / 04期
关键词：
digital signal processing; discrete phase locked loop; lock in amplifier; phase locked loop;
D O I：
10.1016/j.micpro.2003.12.002
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this work, the study, design and development of a Digital Lock In Amplifier (DLIA) with a Digital Signal Processor (DSP) DSP32C from AT&T is presented. To synchronize the DLIA oscillator with external signal, a Discrete Phase Locked Loop (DPLL) is added to the systems. A theoretical introduction of both systems is also presented. The algorithm of the DPLL presented is valid only for constant uniform sampling frequency. (C) 2004 Elsevier B.V. All rights reserved.
引用
收藏
页码：157 / 162
页数：6
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