Digital Beam Former Architecture for Sixteen Elements Planar Phased Array Radar

This paper describes architecture for a digital beam former developed for 16 element phased array radar. The digital beam former architecture includes the complex operations such as down conversion which is done in parallel for the signal coming from each of the antenna elements and the filtering. A high performance FPGA is employed to perform these operations. An echo signal of 5 MHz riding on the IF signal of 60 MHz is down converted digitally to the baseband of the echo signal. The baseband echo signal is then multiplied by the complex weights and then summed to form the beam. The prototype architecture employs 16 bit 125 MS/s ADCs and a very high performance state of the art Xilinx FPGA device Vertex 6vlx240t to form the 112/4/6/9 beams simultaneously. The device used has large number of on chip resources for the parallel processing and the 200MHz clock generator. The complex weights are externally calculated using highly stable Q-R decomposition based recursive least squares algorithm and stored inside the FPGA.