Characterisation and modelling of planar on-chip integrated Peltier elements for highly localised thermal stabilisation and cooling

被引：5
作者：
Wijngaards, DDL [1 ]
Wolffenbuttel, RF [1 ]
机构：
[1] Delft Univ Technol, Dept Elect Engn, Elect Instrumentat Lab, DIMES, NL-2628 CD Delft, Netherlands
来源：
EIGHTEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, PROCEEDINGS 2002 | 2002年
关键词：
on-chip integration; integrated Peltier cooler; polySiGe; modelling; material characterisation;
D O I：
10.1109/STHERM.2002.991354
中图分类号：
O414.1 [热力学];
学科分类号：
摘要：
On-chip integrated Peltier elements are ideally suited for highly localised on-chip thermal stabilisation. The non-idealities are analysed with respect to the impact on device performance and are used to derive the proper performance optimisation criteria. Furthermore, an FEA model is presented which incorporates the Peltier effect itself, as well as the non-idealities. As thermoelectric material, polySiGe is used, because of its good balance between thermoelectric performance and fabrication compatibility. Both the experimental validation of the thermophysical properties, as well as the performance measurements on the first generation integrated Peltier elements are presented and discussed.
引用
收藏
页码：105 / 112
页数：8
相关论文
共 20 条
12