Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

被引：9

作者：

Chouksey, Siddharth ^{[1
]}

Fossum, Jerry G. ^{[1
]}

Behnam, Ashkan ^{[1
]}

Agrawal, Shishir ^{[1
]}

Mathew, Leo ^{[2
]}

机构：

[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA

[2] AND Inc, Austin, TX 78712 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2009年 / 56卷 / 10期

关键词：

Effective channel length; I-ON versus I-OFF; gate-source/drain (G-S/D) underlap; random doping fluctuations (RDFs); source/drain (S/D) lateral doping profile; NONCLASSICAL CMOS DEVICES; GATE;

D O I：

10.1109/TED.2009.2028403

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Nanoscale double-gate (DG) FinFETs with undoped fin bodies are shown to have threshold voltages (V-t) that can be adjusted for independent I-ON and I-OFF control by allowing limited source/drain (S/D) dopants in the channel. S/D engineering of the lateral doping profile in the extension is proposed as a viable means for effecting such channel doping [as well as gate-S/D (G-S/D) underlap] and, thus, adjusting V-t for optimal I-ON/I-OFF in low-power and high-performance applications of nanoscale-FinFET CMOS. Physics-based device simulations, numerical simulations, and measured current-voltage characteristics are used to demonstrate and support the proposed V-t design approach.

引用

页码：2348 / 2353

页数：6

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