Fault latencies of concurrent checking FSMs

被引：4

作者：

Goot, R ^{[1
]}

Levin, I ^{[1
]}

Ostanin, S ^{[1
]}

机构：

[1] Acad Technol Inst, Holon, Israel

来源：

EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS: ARCHITECTURES, METHODS AND TOOLS | 2002年

关键词：

D O I：

10.1109/DSD.2002.1115366

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we introduce concepts. of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM. A method for investigation of latencies for on-line checking FSMs is described. This technique is based on selection of trajectories of the Markov chain, which describes behavior of the fault free FSM as well as the faulty FSM. We also estimate the lowest bound for an average latency. This estimation may be useful at an initial stage of the design when information concerning requirements to the FSM and conditions of its functioning is limited.

引用

页码：174 / 179

页数：6

共 6 条

[1] [Anonymous], FINITE MARKOV CHAINS
[2] Feller W., 1971, INTRO PROBABILITY TH
[3] Lala P. K, 2000, SELF CHECKING FAULT
[4] Self-checking of FPGA-based control units
Levin, I
Sinelnikov, V
[J]. NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 292 - 295
[5] On-line testing for VLSI - A compendium of approaches
Nicolaidis, M
Zorian, Y
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 12 (1-2): : 7 - 20
[6] SHEDLETSKY JJ, 1976, IEEE T COMPUT, V25, P655, DOI 10.1109/TC.1976.1674668

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