A novel fully automated multi-mode scan stitching methodology

With more and more functionality being integrated into System-on-Chip (SoC) designs, the number of test mode configurations required to robustly test a given SoC are also increasing. Test mode configuration is a setup required to test SoC in a particular test methodology like production test, insystem test, stress test and so on. Every test mode configuration can have their unique scan constraints and requires creation of balanced scan chains. These constraints and requirements create a challenge for scan chain allocation, scan chain balancing in every test mode and automation. Existing solutions for these lead to non-scalable scripting, unwanted area overhead and long scan wirelengths due to addition of multimode multiplexers to take into account test mode crossings. This paper describes a new multimode scan stitching methodology which is highly customizable to serve ever growing Design-for-Test (DFT) constraints and scan connection requirements. This paper also introduces the innovative concept of scan groups to give user a simplistic yet powerful user-interface for multimode scan stitching considering test clock domains, power domains, clock edges, scan chain balancing and multimode multiplexers optimizations.