Investigation of BEOL Plasma Process Induced Damage Effect on Gate Oxide

Plasma process induced damage (PID) to thin gate oxide of different thickness was investigated in this paper with antenna test structures to enhance the effect of plasma charging. Gate leakage under Fowler-Nordheim (F-N) stress, threshold voltage, and time dependent dielectric breakdown (TDDB) was applied for gate oxide degrading measurement. It is found that gate oxide with around 5nm electrical oxide thickness (EOT) is more sensitive to plasma process and can be easily revealed with gate leakage. Gate oxide TDDB test with short loop wafers indicated that contact (CT) etching stop layer and back end of line (BEOL) process, especially high density plasma (HDP) chemical vapor deposition (CVD) of inter-metal-dielectric (IMD) plays the main role in oxide damage. These phenomena provide important approaches to reduce PID effect in integrated circuit manufacturing.