A Novel Power-Aware and High Performance Full Adder Cell for Ultra-Low Power Designs

The design of low power VLSI circuit is a challenging task at deep sub-micron technologies. Full adder is a basic key element of many arithmetic circuits like multiplexers, subtracters, dividers, etc... Since the technology is changing at a rapid pace, it is essential to develop and design new methodologies or circuits, which are going to reduce power consumption and worst case delay of circuits. In this regards, this paper is proposing a new circuit design for obtaining full adder functionality of 1-Bit. The proposed full adder is designed with 10-Transistors. The proposed 10-Transistor full adder uses two Low Power XOR gates and a two transistor multiplexer. All the designed circuits in this paper are captured and simulated using Virtuso Schematic Editor and Spectre simulator. These tools are part of Cadence Virtuoso Design Environment provided by Cadence Design Systems. Generic Process Design Kit(GPDK) 45nm technology file is used to get the transistor models. Pre-layout simulation results turn out that the proposed 10-Transistor full adder performance better.