Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance

被引:22
作者
Chen, Qinyu [1 ]
Gao, Chang [2 ,3 ]
Fang, Xinyuan [1 ]
Luan, Haitao [1 ]
机构
[1] Univ Shanghai Sci & Technol, Inst Photon Chips, Shanghai 200093, Peoples R China
[2] Univ Zurich, Inst Neuroinformat, CH-8057 Zurich, Switzerland
[3] Swiss Fed Inst Technol, CH-8057 Zurich, Switzerland
关键词
FPGA; spiking neural network (SNN); workload balance; PROCESSOR;
D O I
10.1109/TCAD.2022.3158834
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Spiking neural networks (SNNs) are developed as a promising alternative to artificial neural networks (ANNs) due to their more realistic brain-inspired computing models. SNNs have sparse neuron firing over time, i.e., spatio-temporal sparsity; thus, they are useful to enable energy-efficient hardware inference. However, exploiting spatio-temporal sparsity of SNNs in hardware leads to unpredictable and unbalanced workloads, degrading the energy efficiency. In this work, we propose an FPGA-based convolutional SNN accelerator called Skydiver that exploits spatio-temporal workload balance. We propose the approximate proportional relation construction (APRC) method that can predict the relative workload channel-wisely and a channel-balanced workload schedule (CBWS) method to increase the hardware workload balance ratio to over 90%. Skydiver was implemented on a Xilinx XC7Z045 FPGA and verified on image segmentation and MNIST classification tasks. Results show improved throughput by 1.4x and 1.2x for the two tasks. Skydiver achieved 22.6KFPS throughput, and 42.4 mu J/image prediction energy on the classification task with 98.5% accuracy.
引用
收藏
页码:5732 / 5736
页数:5
相关论文
共 16 条
[1]   True North: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip [J].
Akopyan, Filipp ;
Sawada, Jun ;
Cassidy, Andrew ;
Alvarez-Icaza, Rodrigo ;
Arthur, John ;
Merolla, Paul ;
Imam, Nabil ;
Nakamura, Yutaka ;
Datta, Pallab ;
Nam, Gi-Joon ;
Taba, Brian ;
Beakes, Michael ;
Brezzo, Bernard ;
Kuang, Jente B. ;
Manohar, Rajit ;
Risk, William P. ;
Jackson, Bryan ;
Modha, Dharmendra S. .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (10) :1537-1557
[2]   A 67.5 μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation [J].
Chen, Qinyu ;
He, Guoqiang ;
Wang, Xinyuan ;
Xu, Jin ;
Shen, Sirui ;
Chen, Hui ;
Fu, Yuxiang ;
Li, Li .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (02) :574-578
[3]   Loihi: A Neuromorphic Manycore Processor with On-Chip Learning [J].
Davies, Mike ;
Srinivasa, Narayan ;
Lin, Tsung-Han ;
Chinya, Gautham ;
Cao, Yongqiang ;
Choday, Sri Harsha ;
Dimou, Georgios ;
Joshi, Prasad ;
Imam, Nabil ;
Jain, Shweta ;
Liao, Yuyun ;
Lin, Chit-Kwan ;
Lines, Andrew ;
Liu, Ruokun ;
Mathaikutty, Deepak ;
Mccoy, Steve ;
Paul, Arnab ;
Tse, Jonathan ;
Venkataramanan, Guruguhanathan ;
Weng, Yi-Hsin ;
Wild, Andreas ;
Yang, Yoonseok ;
Wang, Hong .
IEEE MICRO, 2018, 38 (01) :82-99
[4]   Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey [J].
Deng, Lei ;
Li, Guoqi ;
Han, Song ;
Shi, Luping ;
Xie, Yuan .
PROCEEDINGS OF THE IEEE, 2020, 108 (04) :485-532
[5]   Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs [J].
Fang, Haowen ;
Mei, Zaidao ;
Shrestha, Amar ;
Zhao, Ziyi ;
Li, Yilan ;
Qiu, Qinru .
2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD), 2020,
[6]  
Gao C., 2021, arXiv
[7]   SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks [J].
Gondimalla, Ashish ;
Chesnut, Noah ;
Thottethodi, Mithuna ;
Vijaykumar, T. N. .
MICRO'52: THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2019, :151-165
[8]   Hardware Implementation of Spiking Neural Networks on FPGA [J].
Han, Jianhui ;
Li, Zhaolin ;
Zheng, Weimin ;
Zhang, Youhui .
TSINGHUA SCIENCE AND TECHNOLOGY, 2020, 25 (04) :479-486
[9]   An FPGA Implementation of Deep Spiking Neural Networks for Low-Power and Fast Classification [J].
Ju, Xiping ;
Fang, Biao ;
Yan, Rui ;
Xu, Xiaoliang ;
Tang, Huajin .
NEURAL COMPUTATION, 2020, 32 (01) :182-204
[10]   A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning [J].
Li, Sixu ;
Zhang, Zhaomin ;
Mao, Ruixin ;
Xiao, Jianbiao ;
Chang, Liang ;
Zhou, Jun .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (04) :1543-1552