Adaptive Transaction Scheduling for Transactional Memory Systems

被引:0
|
作者
Yoo, Richard M. [1 ]
Lee, Hsien-Hsin S. [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
来源
SPAA'08: PROCEEDINGS OF THE TWENTIETH ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES | 2008年
关键词
Contention Intensity; Parallelism; Performance; Transaction Effectiveness; Transactional Memory Systems;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Transactional memory systems are expected to enable parallel programming at lower programming complexity, while delivering improved performance over traditional lock-based systems. Nonetheless, there are certain situations where transactional memory systems could actually perform worse. Transactional memory systems can outperform locks only when the executing workloads contain sufficient parallelism. When the workload lacks inherent parallelism, launching excessive transactions can adversely degrade performance. These situations are likely to become dominant in future workloads when large-scale transactions are frequently executed. In this paper, we propose a new paradigm called adaptive transaction scheduling to address this issue. Based on the parallelism feedback from applications, our adaptive transaction scheduler dynamically dispatches and controls the number of concurrently executing transactions. In our case study, we show that our low-cost mechanism not only guarantees that hardware transactional memory systems perform no worse than a single global lock, but also significantly improves performance for both hardware and software transactional memory systems.
引用
收藏
页码:169 / 178
页数:10
相关论文
共 50 条
  • [21] Hardware Transactional Memory for GPU Architectures
    Fung, Wilson W. L.
    Singh, Inderpreet
    Brownsword, Andrew
    Aamodt, Tor M.
    PROCEEDINGS OF THE 2011 44TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO 44), 2011, : 296 - 307
  • [22] Modeling Transactional Memory Workload Performance
    Porter, Donald E.
    Witchel, Emmett
    ACM SIGPLAN NOTICES, 2010, 45 (05) : 349 - 350
  • [23] Performance Pathologies in Hardware Transactional Memory
    Bobba, Jayaram
    Moore, Kevin E.
    Volos, Haris
    Yen, Luke
    Hill, Mark D.
    Swift, Michael M.
    Wood, David A.
    ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS, 2007, : 81 - 91
  • [24] An Analytical Model of Hardware Transactional Memory
    Castro, Daniel
    Romano, Paolo
    Didona, Diego
    Zwaenepoel, Willy
    2017 IEEE 25TH INTERNATIONAL SYMPOSIUM ON MODELING, ANALYSIS, AND SIMULATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS (MASCOTS), 2017, : 221 - 231
  • [25] Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies
    Meunier, Quentin L.
    Petrot, Frederic
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2010, 70 (10) : 1024 - 1041
  • [26] Transactional Auto Scaler: Elastic Scaling of Replicated In-Memory Transactional Data Grids
    Didona, Diego
    Romano, Paolo
    Peluso, Sebastiano
    Quaglia, Francesco
    ACM TRANSACTIONS ON AUTONOMOUS AND ADAPTIVE SYSTEMS, 2014, 9 (02)
  • [27] Virtues and Limitations of Commodity Hardware Transactional Memory
    Diegues, Nuno
    Romano, Paolo
    Rodrigues, Luis
    PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'14), 2014, : 3 - 14
  • [28] An Analytic Model of Optimistic Software Transactional Memory
    Heindl, Armin
    Pokam, Gilles
    Adl-Tabatabai, Ali-Reza
    ISPASS 2009: IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE, 2009, : 153 - +
  • [29] Memory limited algorithms for optimal task scheduling on parallel systems
    Venugopalan, Sarad
    Sinnen, Oliver
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2016, 92 : 35 - 49
  • [30] Unbounded page-based transactional memory
    Chuang, Weihaw
    Narayanasamy, Satish
    Venkatesh, Ganesh
    Sampson, Jack
    Van Biesbrouck, Michael
    Pokam, Gilles
    Colavin, Osvaldo
    Calder, Brad
    ACM SIGPLAN NOTICES, 2006, 41 (11) : 347 - 358