A Low-power Parallel Multiplier Based on Optimized-Equal-Bypassing-Technique

被引：0

作者：

Ding, Yanyu ^{[1
]}

Wang, Deming ^{[1
]}

Hu, Jianguo ^{[1
]}

Tan, Hongzhou ^{[1
]}

机构：

[1] Sun Yat Sen Univ, Inst Electron & Commun, Guangzhou 510275, Guangdong, Peoples R China

来源：

2013 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE AND TECHNOLOGY (ICIST) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power parallel multiplier based on Optimized-Equal-Bypassing-Technique is proposed in this paper. We first exploit a new full adder architecture which is capable of bypassing the addition operation when the two summand signals are equal. Then we optimize the full adder at the transistor level for lower power and smaller area purpose. After that, we employ the novel full adder to structure a parallel multiplier. The multiplier design is implemented with TSMC 0.18um technology and simulated with Hspice tool to estimate power dissipation. The simulation results prove that, compared with other designs in literature, the proposed multiplier shows its significant superiority in terms of power consumption as well as hardware overhead.

引用

页码：563 / 566

页数：4

共 50 条

[11] A ROM based Low-Power Multiplier [J].

Paul, Bipul C. ;

Fujita, Shinobu ;

Kajima, Masaki .

2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 2008, :69-+

[12] Low power and high speed multiplier design with row bypassing and parallel architecture [J].

Kuo, Ko-Chi ;

Chou, Chi-Wen .

MICROELECTRONICS JOURNAL, 2010, 41 (10) :639-650

[13] LOW POWER PARALLEL MULTIPLIER DESIGN USING ROW-COLUMN BYPASSING [J].

Iyappan, G. Iyyakutti ;

Lalitha, V. .

ICMEE 2009: PROCEEDINGS OF THE 2009 INTERNATIONAL CONFERENCE ON MECHANICAL AND ELECTRONICS ENGINEERING, 2010, :225-+

[14] Design of Low-Power Multiplier Using UCSLA Technique [J].

Ravi, S. ;

Patel, Anand ;

Shabaz, Md ;

Chaniyara, Piyush M. ;

Kittur, Harish M. .

ARTIFICIAL INTELLIGENCE AND EVOLUTIONARY ALGORITHMS IN ENGINEERING SYSTEMS, VOL 2, 2015, 325 :119-126

[15] Low power multiplier with bypassing and tree strucuture [J].

Kuo, Ko-Chi ;

Chou, Chi-Wen .

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, :602-+

[16] Designing of Power Optimized Bypassing Array Multiplier in Nanometer Technology [J].

Nirlakalla, Ravi ;

Boothuru, Bhaskara Rao ;

Thota, Subba Rao ;

Babu, M. Rajasekhar ;

Talari, Jayachandra Prasad ;

Krishna, P. Venkata .

GLOBAL TRENDS IN INFORMATION SYSTEMS AND SOFTWARE APPLICATIONS, PT 2, 2012, 270 :277-+

[17] A 145μW 8x8 Parallel Multiplier based on Optimized Bypassing Architecture [J].

Hong, Sunjoo ;

Roh, Taehwan ;

Yoo, Hoi-Jun .

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, :1175-1178

[18] A low-power array multiplier using separated multiplication technique [J].

Han, CY ;

Park, HJ ;

Kim, LS .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2001, 48 (09) :866-871

[19] Low power multiplier designs based on improved column bypassing schemes [J].

Hwang, Ying-Tsung ;

Lin, Jin-Fa ;

Sheu, Ming-Hwa ;

Sheu, Chia-Jen .

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, :594-+

[20] A low-power 2-dimensional bypassing multiplier using 0.35 um CMOS technology [J].

Wang, Chua-Chin ;

Sung, Gang-Neng .

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, :405-+

← 1 2 3 4 5 →