A Low-power Parallel Multiplier Based on Optimized-Equal-Bypassing-Technique

A low power parallel multiplier based on Optimized-Equal-Bypassing-Technique is proposed in this paper. We first exploit a new full adder architecture which is capable of bypassing the addition operation when the two summand signals are equal. Then we optimize the full adder at the transistor level for lower power and smaller area purpose. After that, we employ the novel full adder to structure a parallel multiplier. The multiplier design is implemented with TSMC 0.18um technology and simulated with Hspice tool to estimate power dissipation. The simulation results prove that, compared with other designs in literature, the proposed multiplier shows its significant superiority in terms of power consumption as well as hardware overhead.