Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing

One of the effective techniques to reduce leakage power is power gating. Previously, a Distributed Sleep Transistor Network was proposed to reduce the sleep transistor area for power gating by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current flowing through sleep transistors. In this paper, we propose a new methodology for determining the sizes of sleep transistors of the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop and minimizing the sizes of sleep transistors. We also present mathematical proofs of our theorems and lemmas in detail. Our experimental results show 23.36% sleep transistor area reduction compared to the previous work on average.