Fast DSP Implementation of a Low Complexity LDPC Decoder

被引:0
|
作者
Razi, Mouhcine [1 ]
Benhayoun, Mhammed [1 ]
Mansouri, Anas [1 ]
Madi, Abdessalam Ait [1 ]
Ahaitouf, Ali [1 ]
机构
[1] USMBA Univ, ERSI Lab, Fes, Morocco
关键词
LDPC decoders; Min Sum Algorithm; Horizontal Shuffled Scheduling; DSP implementation;
D O I
10.1109/wits.2019.8723838
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The Belief Propagation (BP) algorithm is known as the most efficient algorithm in terms of convergence speed. But this algorithm has a very high level of computational complexity. The MM Sum Algorithm (MSA) permits to reduce this computational complexity but with some performances degradations. In this paper we recommend a new approach with more simplified algorithm, that allows to get performances near to these of the BP algorithm by adopting a new version of the MSA algorithm. This last uses Horizontal Shuffled (HS) scheduling instead of the usually used flooding scheduling. This algorithm was successfully implemented on the Digital Signal Processor (DSP). The results obtained after implementation show that the proposed version of the MSA algorithm does not only improve the decoding performance but also decreases the number of iterations necessary for the decoding of the LDPC codes.
引用
收藏
页数:5
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