Metal-insulator-semiconductor structure on low-temperature grown GaAs

The metal-insulator-semiconductor (MIS) capacitors on low-temperature grown (LTG) GaAs were made using the jet-vapor-deposition (JVD) silicon nitride as the gate dielectrics. The unpinned JVD-SiN/LTG-GaAs interface was shown by the capacitance-voltage characterization. The observed Fermi level "pinning" in the unannealed samples was caused by the bulk point defects in LTG GaAs. Annealing reduced the bulk defect density in LTG GaAs and revealed the intrinsically unpinned Fermi level at the interface. The result is consistent with the expected unpinning of LTG GaAs surface, and JVD SiN appears to play a critical role to enable this unpinned interface. JVD SiN showed low leakage current (similar to 10 nA/cm(2) at 2 MV/cm) and high breakdown electric field (similar to 9.8 MV/cm), promising for MIS device applications. (c) 2006 American Institute of Physics.