Design and Analysis of a Resistive Sensor Interface With Phase Noise-Energy-Resolution Scalability for a Time-Based Resistance-to-Digital Converter

被引:1
作者
Seo, Dong-Hyun [1 ]
Chatterjee, Baibhab [1 ]
Scott, Sean M. [2 ]
Valentino, Daniel J. [2 ]
Peroulis, Dimitrios [1 ]
Sen, Shreyas [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
[2] Landauer Inc, Chicago, IL USA
来源
FRONTIERS IN ELECTRONICS | 2022年 / 3卷
关键词
resistive sensor; sensor interfacing circuit; resistance-to-digital converter; time-based ADC; low-power; RMS jitter; low-phase noise; energy-resolution scalability; ARRAYS; JITTER;
D O I
10.3389/felec.2022.792326
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article presents the design and analysis of a resistive sensor interface with three different designs of phase noise-energy-resolution scalability in time-based resistance-to-digital converters (RDCs), including test chip implementations and measurements, targeted toward either minimizing the energy/conversion step or maximizing bit-resolution. The implemented RDCs consist of a three-stage differential ring oscillator, which is current starved using the resistive sensor, a differential-to-single-ended amplifier, and digital modules and serial interface. The first RDC design (baseline) included the basic structure of time-based RDC and targeted low-energy/conversion step. The second RDC design (goal: higher-resolution) aimed to improve the rms jitter/phase noise of the oscillator with help of speed-up latches, to achieve high bit-resolution as compared to the first RDC design. The third RDC design (goal: process portability) reduced the power consumption by scaling the technology with the improved phase-noise design, achieving 1-bit better resolution as that of the second RDC design. Using time-based implementation, the RDCs exhibit energy-resolution scalability and consume a measured power of 861 nW with 18-bit resolution in design 1 in TSMC 0.35 mu m technology (with 10 ms read-time, with one readout every second). Measurements of designs 2 and 3 demonstrate power consumption of 19.2 mu W with 20-bit resolution using TSMC 0.35 mu m and 17.6 mu W with 20-bit resolution using TSMC 0.18 mu m, respectively (both with 10 ms read-time, repeated every second). With 30 ms read-time, design 3 achieves 21-bit resolution, which is the highest resolution reported for a time-based ADC. The 0.35-mu m time-based RDC is the lowest-power time-based ADC reported, while the 0.18-mu m time-based RDC with speed-up latch offers the highest resolution. The active chip-area for all three designs is less than 1.1 mm2.
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页数:16
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