FPGA IMPLEMENTATION OF FLOATING-POINT COMPLEX MATRIX INVERSION BASED ON GAUSS-JORDAN ELIMINATION

被引：0
作者：
Moussa, Sherif [1 ,2 ]
Razik, Ahmed M. Abdel [3 ]
Dahmane, Adel Omar [1 ]
Hamam, Habib [4 ]
机构：
[1] Univ Quebec Trois Rivieres, Elec & Comp Eng Dept, Trois Rivieres, PQ GA9 5H7, Canada
[2] Canadian Univ Dubai, Sch Engn, Dubai, U Arab Emirates
[3] Arab Acad Sci Technol & Maritime Transport, Sch Engn, Cairo, Egypt
[4] Univ Moncton, Fac Engn, Moncton, NB E1A 3E9, Canada
来源：
2013 26TH ANNUAL IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE) | 2013年
关键词：
MIMO; OFDM; FPGA; matrix inversion;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This work presents the architecture of an optimized complex matrix inversion using GAUSS-JORDAN elimination (GJ-elimination) on FPGA with single precision floating-point representation to be used in MIMO-OFDM receiver. This module consists of single precision floating point arithmetic components and control unit which perform the GJ-elimination algorithm. The proposed architecture performs the GJ-elimination for complex matrix element by element. Only critical arithmetic operations are calculated to get the needed values without performing all the arithmetic operations of the GJ-elimination algorithm. This results in a reduced hardware resources and execution time.
引用
收藏
页码：557 / 560
页数：4
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