FPGA IMPLEMENTATION OF FLOATING-POINT COMPLEX MATRIX INVERSION BASED ON GAUSS-JORDAN ELIMINATION

This work presents the architecture of an optimized complex matrix inversion using GAUSS-JORDAN elimination (GJ-elimination) on FPGA with single precision floating-point representation to be used in MIMO-OFDM receiver. This module consists of single precision floating point arithmetic components and control unit which perform the GJ-elimination algorithm. The proposed architecture performs the GJ-elimination for complex matrix element by element. Only critical arithmetic operations are calculated to get the needed values without performing all the arithmetic operations of the GJ-elimination algorithm. This results in a reduced hardware resources and execution time.