High performance VHDL FIR filter structure for symbol timing system implemented on FPGA

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. Digital filters are necessary in transmitter / receiver side and FIR filters are often chosen for their beneficial properties against 1W filters. Symbol synchronization subsystem also maintains digital filters for interpolation purpose. The goal of this paper is to develop efficient fully parallel FIR filter structure in VHDL language for symbol synchronization purpose. The first part of this paper is focused on formulation distributed arithmetic technique for proposed FIR filter. The second part describes incorporation of this filter to symbol synchronization subsystem. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size. The result of RTL synthesis on FPGA is finally discussed.