GIVING TEXT ANALYTICS A BOOST

被引：11
|
作者：
Polig, Raphael [1 ]
Atasu, Kubilay [1 ]
Chiticariu, Laura [2 ]
Hagleitner, Christoph [3 ]
Hofstee, H. Peter [4 ]
Reiss, Frederick R. [4 ]
Zhu, Huaiyu [4 ]
Sitaridi, Eva [5 ]
机构：
[1] IBM Res, Zurich Res Lab, Zurich, Switzerland
[2] IBM Res, Intelligent Informat Syst Grp, Zurich, Switzerland
[3] IBM Res, Accelerator Technol Grp, Zurich, Switzerland
[4] IBM Res, Zurich, Switzerland
[5] Columbia Univ, Dept Comp Sci, New York, NY 10027 USA
来源：
IEEE MICRO | 2014年 / 34卷 / 04期
关键词：
Big data; Computer architecture; Field programmable gate arrays; Instruction sets; Text mining; Text processing;
D O I：
10.1109/MM.2014.69
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
TRADITIONAL SERVER ARCHITECTURES CANNOT ANALYZE BIG DATA EFFICIENTLY. BY USING A STREAMING HARDWARE ACCELERATOR IMPLEMENTED IN RECONFIGURABLE LOGIC, THE AUTHORS CAN IMPROVE THE THROUGHPUT OF SYSTEMT'S INFORMATION EXTRACTION QUERIES BY AN ORDER OF MAGNITUDE. SUCH A SYSTEM CAN BE DEPLOYED BY EXTENDING SYSTEMT'S EXISTING COMPILATION FLOW AND USING A MULTITHREADED COMMUNICATION INTERFACE THAT CAN UTILIZE THE ACCELERATOR'S BANDWIDTH.
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页码：6 / 14
页数：9
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