New single-clock CMOS latches and flip-flops with improved speed and power savings - Comment

被引：8

作者：

Blair, GM

机构：

[1] Univ of Edinburgh, Edinburgh

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 10期

关键词：

circuit design; CMOS logic circuits; edge-triggered latch; latch design;

D O I：

10.1109/4.634673

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In a recent paper,(1) Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is developed from one of the semistatic versions.

引用

页码：1610 / 1611

页数：2