SiO2/4H-SiC Interface Traps Effects on the Input Capacitance of DMOSFET

被引：0
|
作者：
Licciardo, Gian-Domenico [1 ]
Di Benedetto, Luigi [1 ]
机构：
[1] Univ Salerno, Dept Ind Engn, Via Giovanni Paolo 2,132, I-84084 Fisciano, SA, Italy
来源：
2016 11TH INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES & MICROSYSTEMS (ASDAM) | 2016年
关键词：
POTENTIAL BARRIER; MODEL; MOSFETS; JFET;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, an analytical model is presented to describe the input capacitance of Power-MOSFETs in 4H poly type of Silicon Carbide (4H-SiC). In order to provide an instrument for accurate interpretations of C-V measurements and for a deeper understanding of the device operations, the model describes the charge variations induced by the presence of the oxide-semiconductor interface trapped charge. Their energy dependence has been accounted to describe the charge dynamics into the channel and the accumulation layer and proved by comparisons with numerical simulations.
引用
收藏
页码：19 / 22
页数：4
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