AES hardware implementation in FPGA for algorithm acceleration purpose

被引：23

作者：

Gielata, Artur ^{[1
]}

Russek, Pawel ^{[1
]}

Wiatr, Kazimierz ^{[1
]}

机构：

[1] AGH UST Dept Elect, PL-30059 Krakow, Poland

来源：

ICSES 2008 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS, CONFERENCE PROCEEDINGS | 2008年

关键词：

cryptography; AES; FPGA; hardware acceleration;

D O I：

10.1109/ICSES.2008.4673377

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we investigate hardware implementation of AES-128 cipher standard on FPGA technology. In many network applications software implementations of cryptographic algorithms are slow and inefficient. To solve that problems custom architecture in reconfigurable hardware was proposed to speed up the performance and flexibility of Rijndael algorithm implementation. We aimed to achieve the maximum speed and efficiency of cipher process, therefore pipeline architecture of AES module was proposed. The investigations involved simulations and synthesis of VHDL code utilizing Virtex4 series of Xilinx.

引用

页码：137 / 140

页数：4