Low voltage CMOS full adder cells

被引：7

作者：

Radhakrishnan, D ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Appl Sci, Div Comp Engn, Singapore 639798, Singapore

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 21期

关键词：

D O I：

10.1049/el:19991282

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A formal design procedure for realising a minimal transistor CMOS XOR-XNOR cell using pass networks is presented that successfully scales down with power supply voltage and fully compensates for the threshold voltage drop in MOS transistors. A full adder using this cell is also presented.

引用

页码：1792 / 1794

页数：3

共 6 条

[1]

Lee HH, 1997, P IEEE INT ASIC C&E, P225, DOI 10.1109/ASIC.1997.617010

[2] DESIGN OF CMOS CIRCUITS [J].

RADHAKRISHNAN, D .

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1991, 138 (01) :83-90

[3]

RADHAKRISHNAN D, 1983, THESIS U IDAHO MOSCO

[4] A new full adder cell for low-power applications [J].

Shams, AM ;

Bayoumi, MA .

PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, :45-49

[5] NEW EFFICIENT DESIGNS FOR XOR AND XNOR FUNCTIONS ON THE TRANSISTOR LEVEL [J].

WANG, JM ;

FANG, SC ;

FENG, WS .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (07) :780-786

[6]

WESTE NHE, 1993, PRINCIPLES CMOS VLSI

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