Variable packet size buffered crossbar (CICQ) switches

被引:31
作者
Katevenis, M [1 ]
Passas, G [1 ]
Simos, D [1 ]
Papaefstathiou, I [1 ]
Chrysos, N [1 ]
机构
[1] Fdn Res & Technol Hellas, FORTH, Inst Comp Sci, ICS, GR-71110 Iraklion, Crete, Greece
来源
2004 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-7 | 2004年
关键词
D O I
10.1109/ICC.2004.1312669
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
One of the most widely used architectures for packet switches is the crossbar. A special version of it is the buffered crossbar, where small buffers are associated with the crosspoints; this simplifies scheduling and improves its efficiency and QoS capabilities to the point where the switch needs no internal speedup. Furthermore, by supporting variable length packets throughout a buffered crossbar: (a) there is no need for segmentation and reassembly (SAR) circuits; (b) no speedup is necessary to support SAR; and (c) synchronization between the input and output clock domains is simplified. In turn, the lack of SAR and speedup mean that no output queues are needed, either. In this paper we present an architecture, a chip layout and cost analysis, and a performance evaluation of such a 300 Gbps buffered crossbar operating on variable-size packets. The proposed organization is simple yet powerful, can be implemented using modern technology, and, as the performance results demonstrate, it clearly outperforms unbuffered crossbars.
引用
收藏
页码:1090 / 1096
页数:7
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