High Performance Parallelization of Boyer-Moore Algorithm on Many-Core Accelerators

被引:0
|
作者
Jeong, Yosang [1 ]
Lee, Myungho [1 ]
Nam, Dukyun [2 ]
Kim, Jik-Soo [2 ]
Hwang, Soonwook [2 ]
机构
[1] Myongji Unviers, Dept Comp Sci & Engn, 116 Myongji Ro, Yongin, Kyung Ki Do, South Korea
[2] Korea Inst Sci & Technol Informat, Supercomp R&D Ctr, Daejeon, South Korea
关键词
Boyer-Moore algorithm; many-core accelerator; parallelization; dynamic scheduling; multithreading; algorithmic cascading;
D O I
10.1109/ICCAC.2014.20
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Boyer-Moore (BM) algorithm is a single pattern string matching algorithm. It is considered as the most efficient string matching algorithm and used in many applications. The algorithm first calculates two string shift rules based on the given pattern string in the preprocessing phase. These rules help skip parts of the target input string where there is no match to be found. Using the two shift rules, pattern matching operations are performed against the target input sting in the second phase. The second phase is a time consuming process and needs to be parallelized to achieve the high performance string matching. In this paper, we parallelize the BM algorithm on the latest many-core accelerators such as the Intel Xeon Phi and the Nvidia Tesla K20 GPU, along with the general-purpose multi-core processors. We partition the target input data amongst multiple threads for parallel execution. Data lying on the threads' boundaries need to be copied redundantly so that the pattern string lying on the boundary can be found. As the target length increases, the algorithm incurs increased matching operations. Also, as the pattern length increases, the number of possible matches decreases. This can potentially lead to the unbalanced workload distribution among threads. Furthermore, the redundant data copy significantly overloads the on-chip shared memories of the GPU for a large number of threads. We use the dynamic scheduling and the multithreading techniques to solve the load balancing problem. We also use the algorithmic cascading technique to reduce the burden on the shared memories of the GPU. Our parallel implementation leads to similar to 17-times speedup on the Xeon Phi and similar to 45-times speedup on the Nvidia Tesla K20 GPU compared with a serial implementation on the host Intel Xeon processor.
引用
收藏
页码:265 / 272
页数:8
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