CNN-Based Layout Segment Classification for Analysis of Layout-Induced Failures

被引:4
作者
Nagamura, Yoshikazu [1 ]
Ide, Takashi [1 ]
Arai, Masayuki [2 ]
Fukumoto, Satoshi [3 ]
机构
[1] Renesas Elect Corp, Anal & Evaluat Technol Dept, Ibaraki 3128511, Japan
[2] Nihon Univ, Coll Ind Technol, Dept Math Informat Engn, Narashino, Chiba 2758575, Japan
[3] Tokyo Metropolitan Univ, Dept Elect Engn & Comp Sci, Hino, Tokyo 1910065, Japan
基金
日本学术振兴会;
关键词
Layout; Large scale integration; Image segmentation; Training; Training data; Silicon; Substrates; CNN; design for manufacturing; failure analysis; image classification; machine learning; neural networks;
D O I
10.1109/TSM.2020.3029049
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Physical failure analysis (PFA) specifies layout designs that affect large-scale integration (LSI) failure. Because of their capability and cost-effectiveness, convolutional neural networks (CNNs) have been applied to LSI layout analysis. However, the information on failure for root cause analyses is generally limited. Moreover, information over a large area, which includes many geometries, is required to understand the effects of a layout on failure. These problems pose challenges in training the CNN models to achieve high accuracy for layout segment classification. In this study, we propose a scheme for layout segment classification that uses CNN to analyze the effects of layout on failure. Thus, multiple segment images of LSI layouts are used as inputs, and the outputs of CNN models are used to classify the input images as either risk or non-risk segments. First, we evaluated a simple 3-layer model, and then a 15-layer model fine-tuned using the transfer learning of the VGG16 model. The 15-layer model outperformed the 3-layer model for classifying the LSI layout segments. From a cross-validation of the 15-layer model, a true positive rate of >80% and a false positive rate of <10% are obtained for extracting layout regions related to actual defects. The outputs of the CNN models from the input layout segment demonstrate similarity with the defective layouts. In the regional layouts across the LSI chips, the contour plot of model outputs is visualized as a hazard map of failures. This information is necessary for additional failure cause analyses.
引用
收藏
页码:597 / 605
页数:9
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