CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors

Approximate computing is one of the emerging concepts in multimedia applications like image processing applications. In the research world, it is getting more attention from researchers. Because of sacrificing a smaller scale in the accuracy of the design, it reduces the circuit parameters like area complexity, delay, and power. The purpose of this work is to survey the Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementation of modified Dadda multiplier architecture using various approximate 4:2 compressor designs presented for the last few decades. Based on implementation outcomes, this survey examines the approximate modified Dadda multiplier design performance for its closeness to the exact computation. In addition, the comparison is carried out based on approximate 4:2 compressors performance, an error rate of the particular design, the accuracy analysis metrics of approximate multiplier and its area utilization, power consumption, and delay.