A multilevel memristor-CMOS memory cell as a ReRAM

被引:35
作者
Rabbani, Payam [1 ]
Dehghani, Rasoul [1 ]
Shahpari, Nima [2 ]
机构
[1] Isfahan Univ Technol, Esfahan, Iran
[2] Isfahan Univ, Esfahan, Iran
关键词
Memristor; Multilevel storage; Hybrid structure; Nonvolatile memory; DEVICE;
D O I
10.1016/j.mejo.2015.10.006
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Memristor is a newly invented device and since it has been found, has drawn a lot of attention from integrated electronics designers because of its nanometer size and special electrical properties. One of the most significant characteristics of a memristor is its memory property. In this paper, a nonvolatile memory cell, based on the hybrid structure of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) is proposed which can be used as a resistive Random Access Memory (RAM). This cell can store data in either binary or non-binary (multilevel) logic, increasing the amount of storable data per square area of a memory chip by increasing the levels of stored data. The methodologies of work with this multilevel logic and data saving and retention are discussed and the suitable one is chosen. The proposed memory cell has a read time comparable to other RAMs and flash memories and percent's of area reduction per two bits of data with at least 50% increase in reading speed - for ternary logic - per data. Power consumption is also reduced. The buffer for this cell corresponding to ternary logic is also presented. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1283 / 1290
页数:8
相关论文
共 50 条
  • [41] Hybrid CMOS/Memristor Circuits
    Strukov, D. B.
    Stewart, D. R.
    Borghetti, J.
    Li, X.
    Pickett, M.
    Ribeiro, G. Medeiros
    Robinett, W.
    Snider, G.
    Strachan, J. P.
    Wu, W.
    Xia, Q.
    Yang, J. Joshua
    Williams, R. S.
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1967 - 1970
  • [42] Interface Engineering for 3-Bit per Cell Multilevel Resistive Switching in AlN Based Memristor
    Mohanty, Srikant Kumar
    Reddy, Poshan Kumar
    Prasad, Om Kumar
    Wu, Chien-Hung
    Chang, Kow-Ming
    Lin, Jia-Chuan
    IEEE ELECTRON DEVICE LETTERS, 2021, 42 (12) : 1770 - 1773
  • [43] Hybrid CMOS-Memristor based FPGA Architecture
    Sampath, Madankumar
    Mane, Pravin S.
    Ramesha, C. K.
    2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2015,
  • [44] Multilevel resistive switching memristor based on silk fibroin/graphene oxide with image reconstruction functionality
    Liu, Shubin
    Cheng, Yu
    Han, Fang
    Fan, Suna
    Zhang, Yaopeng
    CHEMICAL ENGINEERING JOURNAL, 2023, 471
  • [45] A Memristor-based Memory Cell Using Ambipolar Operation
    Junsangsri, Pilin
    Lombardi, Fabrizio
    2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2011, : 148 - 153
  • [46] Memristor Based Ternary Content Addressable Memory (MTCAM) Cell
    Dhiman, Rajni
    Kaur, Manjit
    Singh, Gurmohan
    2015 2ND INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN ENGINEERING & COMPUTATIONAL SCIENCES (RAECS), 2015,
  • [47] Delayed Switching Applied to Memristor Content Addressable Memory Cell
    Chen, Wanlong
    Yang, Xiao
    Wang, Frank Z.
    WORLD CONGRESS ON ENGINEERING - WCE 2013, VOL I, 2013, : 354 - 357
  • [48] A Hardware Architecture for Columnar-Organized Memory Based on CMOS Neuron and Memristor Crossbar Arrays
    Shamsi, Jafar
    Mohammadi, Karim
    Shokouhi, Shahriar B.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (12) : 2795 - 2805
  • [49] A New CMOS Based Memristor Implementation
    Yener, Suayb
    Kuntman, Hakan
    2012 INTERNATIONAL CONFERENCE ON APPLIED ELECTRONICS, 2012, : 345 - 348
  • [50] Programmable CMOS/Memristor Threshold Logic
    Gao, Ligang
    Alibart, Fabien
    Strukov, Dmitri B.
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2013, 12 (02) : 115 - 119