A multilevel memristor-CMOS memory cell as a ReRAM

被引:35
作者
Rabbani, Payam [1 ]
Dehghani, Rasoul [1 ]
Shahpari, Nima [2 ]
机构
[1] Isfahan Univ Technol, Esfahan, Iran
[2] Isfahan Univ, Esfahan, Iran
关键词
Memristor; Multilevel storage; Hybrid structure; Nonvolatile memory; DEVICE;
D O I
10.1016/j.mejo.2015.10.006
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Memristor is a newly invented device and since it has been found, has drawn a lot of attention from integrated electronics designers because of its nanometer size and special electrical properties. One of the most significant characteristics of a memristor is its memory property. In this paper, a nonvolatile memory cell, based on the hybrid structure of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) is proposed which can be used as a resistive Random Access Memory (RAM). This cell can store data in either binary or non-binary (multilevel) logic, increasing the amount of storable data per square area of a memory chip by increasing the levels of stored data. The methodologies of work with this multilevel logic and data saving and retention are discussed and the suitable one is chosen. The proposed memory cell has a read time comparable to other RAMs and flash memories and percent's of area reduction per two bits of data with at least 50% increase in reading speed - for ternary logic - per data. Power consumption is also reduced. The buffer for this cell corresponding to ternary logic is also presented. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1283 / 1290
页数:8
相关论文
共 50 条
  • [21] Low-power hybrid memristor-CMOS spiking neuromorphic STDP learning system
    Maranhao, Gabriel
    Guimaraes, Janaina Goncalves
    IET CIRCUITS DEVICES & SYSTEMS, 2021, 15 (03) : 237 - 250
  • [22] A design of HTM spatial pooler for face recognition using Memristor-CMOS hybrid circuits
    Ibrayev, Timur
    James, Alex Pappachen
    Merkel, Cory
    Kudithipudi, Dhireesha
    2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1254 - 1257
  • [23] Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons
    Tien Van Nguyen
    Khoa Van Pham
    Min, Kyeong-Sik
    MATERIALS, 2019, 12 (06)
  • [24] Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation
    Dong, Zhekang
    Qi, Donglian
    He, Yufei
    Xu, Zhao
    Hu, Xiaofang
    Duan, Shukai
    INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS, 2018, 28 (12):
  • [25] A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA
    Guo, Yanwen
    Wang, Xiaoping
    Zeng, Zhigang
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 36 (12) : 2144 - 2148
  • [26] Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage
    Ishizaka, Mamoru
    Shintani, Michihiro
    Inoue, Michiko
    2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS), 2018, : 167 - 172
  • [27] Hybrid memristor-CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks
    Zhang, Xumeng
    Lu, Jian
    Wang, Zhongrui
    Wang, Rui
    Wei, Jinsong
    Shi, Tuo
    Dou, Chunmeng
    Wu, Zuheng
    Zhu, Jiaxue
    Shang, Dashan
    Xing, Guozhong
    Chan, Mansun
    Liu, Qi
    Liu, Ming
    SCIENCE BULLETIN, 2021, 66 (16) : 1624 - 1633
  • [28] A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory
    Yilmaz, Yalcin
    Mazumder, Pinaki
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (06) : 1016 - 1027
  • [29] Design of memristor based low power and highly reliable ReRAM cell
    Pal, Soumitra
    Bose, Subhankar
    Islam, Aminul
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2022, 28 (03): : 793 - 807
  • [30] On Defect Oriented Testing for Hybrid CMOS/memristor Memory
    Haron, Nor Zaidi
    Hamdioui, Said
    Haron, Nor Zaidi
    2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 353 - 358