The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA

Packet classification has been recognized as one of the most significant functions in contemporary network infrastructures. Furthermore, a number of modern applications such as IoTs contain very strict constraints on the latency of network transmissions. This paper presents the design and implementation of a novel packet classification based on FPGA architecture. The proposed design contains a Latency Compression Scheme (LCS) to achieve the low-latency packet processing. Furthermore, this structure supports 12-tuple fields for the modern Internet traffics. The experimental results show that the proposed packet classification scheme reduces the delay of packet processing by 2.18 x compared to the state-of-the-art works.