A Prolonged Discharge Time ESD Power-rail Clamp Circuit Structure with Strong Ability to Prevent False Triggering

被引：0

作者：

Cao, Jian ^{[1
,2
]}

Xue, Xiangxiang ^{[1
]}

Wang, Yuan ^{[2
]}

Lu, Guangyi ^{[2
]}

Zhang, Xing ^{[1
,2
]}

机构：

[1] Peking Univ, Sch Software & Microelect, Beijing 102600, Peoples R China

[2] Peking Univ, Key Lab Microelect Devices & Circuits MoE, Beijing 100871, Peoples R China

来源：

2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2016年

关键词：

ESD; power-rail clamp circuit; leakage current; anti-false triggering; discharge time; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new reliable Electrostatic Discharge (ESD) power-rail clamp circuit has been proposed in this paper. The new circuit structure has achieved good results in reducing leakage current, anti-false triggering, increasing discharge transistor's turn on time. During the ESD event, the proposed circuit has a discharge time of 755.22ns, which is about 6.74 times that of conventional R-C power-rail clamp circuit. Besides, the leakage current of whole circuit eventually stabilizes at a lower level of 46.50nA.

引用

页码：1291 / 1293

页数：3

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