Circuit Reliability Analysis Using Signal Reliability Correlations

被引:6
作者
Cai, Jinchen [1 ]
Chen, Chunhong [1 ]
机构
[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON, Canada
来源
2017 IEEE INTERNATIONAL CONFERENCE ON SOFTWARE QUALITY, RELIABILITY AND SECURITY COMPANION (QRS-C) | 2017年
关键词
Combinational circuits; reliability analysis; signal probability correlation; signal reliability correlation; large-scale circuits; LOGIC-CIRCUITS; DESIGN;
D O I
10.1109/QRS-C.2017.34
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
With continuous scaling of CMOS technology, reliability is becoming one of key issues for integrated circuit designs. This paper presents an effective reliability analysis method for combinational circuits by using signal reliability correlations. Signal probabilities in the error-free version of unreliable circuits are assumed to be available prior to using the proposed method, as they can be obtained from many standard CAD tools. Simulation results on benchmark circuits show that the proposed method outperforms many existing methods in terms of efficiency and/or accuracy levels.
引用
收藏
页码:171 / 176
页数:6
相关论文
共 16 条
[1]  
Amerasekera E.A., 1997, FAILURE MECH SEMICON
[2]  
[Anonymous], UCBERLM9241
[3]   Reliability analysis of large circuits using scalable techniques and tools [J].
Bhaduri, Debayan ;
Shukla, Sandeep K. ;
Graham, Paul S. ;
Gokhale, Maya B. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (11) :2447-2460
[4]  
BRYANT RE, 1986, IEEE T COMPUT, V35, P677, DOI 10.1109/TC.1986.1676819
[5]   Reliability Analysis of Logic Circuits [J].
Choudhury, Mihir R. ;
Mohanram, Kartik .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (03) :392-405
[6]  
Ercolani S., 1989, Proceedings of the 1st European Test Conference (IEEE Cat. No.89CH2696-3), P132, DOI 10.1109/ETC.1989.36234
[7]   Reliability evaluation of logic circuits using probabilistic gate models [J].
Han, Jie ;
Chen, Hao ;
Boykin, Erin ;
Fortes, Jose .
MICROELECTRONICS RELIABILITY, 2011, 51 (02) :468-476
[8]   Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits [J].
Huang, Ching-Yi ;
Yu, Zheng-Shan ;
Hu, Yung-Chun ;
Tsou, Tung-Chen ;
Wang, Chun-Yao ;
Chen, Yung-Chih .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (04) :615-628
[9]   Accurate and Efficient Estimation of Logic Circuits Reliability Bounds [J].
Ibrahim, Walid ;
Shousha, Marwa ;
Chinneck, John W. .
IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (05) :1217-1229
[10]   Accurate reliability evaluation and enhancement via probabilistic transfer matrices [J].
Krishnaswamy, S ;
Viamontes, GF ;
Markov, IL ;
Hayes, JP .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, :282-287