A Software Pipelining Algorithm in High-Level Synthesis for FPGA Architectures

被引：0

作者：

Gao, Lei ^{[1
]}

Zaretsky, David ^{[2
]}

Mittal, Gaurav ^{[2
]}

Schonfeld, Dan ^{[1
]}

Banerjee, Prith ^{[2
]}

机构：

[1] Univ Illinois, 851 S Morgan St, Chicago, IL 60607 USA

[2] Binachip Inc, Chicago, IL 60601 USA

来源：

ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 | 2009年

关键词：

Software pipelining; Modulo Scheduling; circular dependency; memory lifetime hole; memory address aliasing;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the non-pipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.

引用

页码：297 / +

页数：2

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