Fully Digital Grid Synchronization Under Harmonics and Unbalanced Conditions

被引：9
作者：
Bai, Yu [1 ]
Guo, Xiaoqiang [1 ]
Wang, Baocheng [1 ]
Li, Yongjian [2 ]
机构：
[1] Yanshan Univ, Dept Elect Engn, Qinhuangdao 066004, Hebei, Peoples R China
[2] Hebei Univ Technol, State Key Lab Reliabil & Intelligence Elect Equip, Tianjin 300130, Peoples R China
来源：
IEEE ACCESS | 2019年 / 7卷
基金：
中国国家自然科学基金;
关键词：
Grid synchronization; phase-locked loop; digital phase-locked loop; PHASE-LOCKED LOOP; IMPROVEMENT; PLL; OPERATION; EPLL;
D O I：
10.1109/ACCESS.2019.2933564
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
For the grid-connected system, the unbalanced and harmonic components of three-phase grid voltage have a significant impact on the accuracy of grid synchronization. And the positive, negative sequences, harmonics, as well as dc component of the three-phase grid voltage are difficult to separate and extract in a fast and precise way. In this paper, a new fully digital phase-locked loop (FDPLL) is proposed. Compared with the existing continuous-domain methods, it is simple to implement, and able to quickly and accurately extract the positive and negative sequence components for grid synchronization. In order to verify the effectiveness and feasibility of the proposed method, the time-domain simulation is carried out. Finally, the feasibility of the proposed method is experimentally verified with a 32-bit floating-point TMS320F28335 DSP. The experimentally results verify the effectiveness of the proposed solution.
引用
收藏
页码：109969 / 109981
页数：13
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