Test generation games from formal specifications

被引：8

作者：

Banerjee, Ansuman ^{[1
]}

Pal, Bhaskar ^{[1
]}

Das, Sayantan ^{[1
]}

Kumar, Abhijeet ^{[1
]}

Dasgupta, Pallab ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

verification; test generation; vacuity; realizability;

D O I：

10.1109/DAC.2006.229273

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present methods for automatic test generation from formal specifications. These are used to create intelligent test benches that are able to cover corner case behaviors in much less time. We have developed a prototype tool for intelligent test generation within the layered test bench architecture proposed in RVM. We present results on verification IPs of standard bus protocols to show the effectiveness of our approach.

引用

页码：827 / +

页数：2