A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

被引：57
作者：
Xanthopoulos, T [1 ]
Chandrakasan, AP [1 ]
机构：
[1] MIT, Cambridge, MA 02139 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 05期
关键词：
discrete cosine transform; low power DSP; video compression;
D O I：
10.1109/4.841502
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This work describes the implementation of a discrete cosine transform (DCT) core compression system targetted to low-power video (MPEG2 MP@ML) and still-image (JPEG) applications. It exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context along with standard voltage scaling techniques such as pipelining and parallelism, The first method dynamically minimizes the bitwidth of arithmetic operations in the presence of data spatial correlation. The second method trades off power dissipation and image compression quality (arithmetic precision.) The chip dissipates 4.38 mW at 14 MHz and 1.56 V.
引用
收藏
页码：740 / 750
页数：11
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