Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

被引:24
作者
Cocorullo, G. [1 ]
Corsonello, P. [1 ]
Frustaci, F. [1 ]
Perri, S. [1 ]
机构
[1] Univ Calabria, Dept Informat Modeling Elect & Syst Engn, I-87036 Arcavacata Di Rende, Italy
关键词
BCD adders; decimal arithmetic; quantum-dot cellular automata (QCA);
D O I
10.1109/TCSII.2016.2580901
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Among the emerging technologies recently proposed as alternatives to the classic CMOS, quantum-dot cellular automata (QCA) is one of the most promising solutions to design ultralow-power and very high speed digital circuits. Efficient QCA-based implementations have been demonstrated for several binary and decimal arithmetic circuits, but significant improvements are still possible if the logic gates inherently available within the QCA technology are smartly exploited. This brief proposes a new approach to design QCA-based BCD adders. Exploiting innovative logic formulations and purpose-designed QCA modules, computational speed significantly higher than existing counterparts is achieved without sacrificing either the occupied area or the cell count.
引用
收藏
页码:575 / 579
页数:5
相关论文
共 28 条
[1]  
[Anonymous], SILMINDS DFP ADD UN
[2]  
[Anonymous], 2015, SPARC64 X X SPEC VER
[3]  
Bayrakçi AA, 2007, IEEE INT CONF ASAP, P266
[4]   Adder designs and analyses for quantum-dot cellular automata [J].
Cho, Heumpil ;
Swartzlander, Earl E., Jr. .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2007, 6 (03) :374-383
[5]   Adder and Multiplier Design in Quantum-Dot Cellular Automata [J].
Cho, Heumpil ;
Swartzlander, Earl E., Jr. .
IEEE TRANSACTIONS ON COMPUTERS, 2009, 58 (06) :721-727
[6]   IBM POWER6 accelerators:: VMX and DFU [J].
Eisen, L. ;
Ward, J. W., III ;
Tast, H. -W. ;
Maeding, N. ;
Leenstra, J. ;
Mueller, S. M. ;
Jacobi, C. ;
Preiss, J. ;
Schwarz, E. M. ;
Carlough, S. R. .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2007, 51 (06) :663-683
[7]   Quantum-Dot Cellular Automata Serial Decimal Adder [J].
Gladshtein, Michael .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2011, 10 (06) :1377-1382
[8]   High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings [J].
Han, Liu ;
Ko, Seok-Bum .
IEEE TRANSACTIONS ON COMPUTERS, 2013, 62 (05) :956-968
[9]  
IEEE, 2008, 7541985 IEEE
[10]   High-speed multioperand decimal adders [J].
Kenney, RD ;
Schulte, MJ .
IEEE TRANSACTIONS ON COMPUTERS, 2005, 54 (08) :953-963