A fully integrated 40-Gbit/s clock and data recovery circuit using InP/InGaAs HBTs

被引：8

作者：

Nosaka, H ^{[1
]}

Sano, E ^{[1
]}

Ishii, K ^{[1
]}

Ida, M ^{[1
]}

Kurishima, K ^{[1
]}

Enoki, T ^{[1
]}

Shibata, T ^{[1
]}

机构：

[1] NTT Corp, NTT Photon Labs, Atsugi, Kanagawa 2430198, Japan

来源：

2002 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3 | 2002年

关键词：

D O I：

10.1109/MWSYM.2002.1011564

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An integrated clock and data recovery (CDR) circuit is a key element for optical communication systems at 40 Gbit/s. We present a fully integrated 40-Gbit CDR circuit fabricated using InP/InGaAs HBTs. The circuit contains a linear-type phase detector and a full-data-rate voltage-controlled oscillator. Error-free operation and wide eye opening were obtained for 40-Gbit/s pseudorandom bit sequence (PRBS) with a length of 2(23)-1. The fabricated IC dissipates 1.71 W at a supply voltage of -4.5V.

引用

页码：83 / 86

页数：4

共 11 条

[1]

GEORGIOU G, 2001, 2001 IEEE GAAS IC S, P93

[2] Undoped-emitter InP/InGaAs HBTs for high-speed and low-power applications [J].

Ida, M ;

Kurishima, K ;

Nakajima, H ;

Watanabe, N ;

Yamahata, S .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :854-856

[3] 3.5-Gb/sx4-Ch Si bipolar LSI's for optical interconnections [J].

Ishihara, N ;

Fujita, S ;

Togashi, M ;

Hino, S ;

Arai, Y ;

Tanaka, N ;

Kobayashi, Y ;

Akazawa, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (12) :1493-1501

[4] VERY-HIGH-SPEED SI BIPOLAR STATIC FREQUENCY-DIVIDERS WITH NEW T-TYPE FLIP-FLOPS [J].

ISHII, K ;

ICHINO, H ;

TOGASHI, M ;

KOBAYASHI, Y ;

YAMAGUCHI, C .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (01) :19-24

[5] A complete GaAs HEMT single chip data receiver for 40 Gbit/s data rates [J].

Lang, M ;

Wang, ZG ;

Thiede, A ;

Lienhart, H ;

Jakobus, T ;

Bronner, W ;

Hornung, J ;

Hülsmann, A .

GAAS IC SYMPOSIUM - 20TH ANNUAL, TECHNICAL DIGEST 1998, 1998, :55-58

[6]

Murata K, 2000, IEICE T ELECTRON, VE83C, P1166

[7] Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InPHEMT technology [J].

Murata, K ;

Sano, K ;

Sano, E ;

Sugitani, S ;

Enoki, T .

ELECTRONICS LETTERS, 2001, 37 (20) :1235-1237

[8]

Reinhold M., 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), P84, DOI 10.1109/ISSCC.2001.912557

[9]

Sano E, 1999, IEICE T ELECTRON, VE82C, P2000

[10] 40Gbit/s decision IC using InP/InGaAs composite-collector heterojunction bipolar transistors [J].

Sano, E ;

Nakajima, H ;

Watanabe, N ;

Yamahata, S .

ELECTRONICS LETTERS, 1999, 35 (14) :1194-1195

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