A Low-Power All-Digital PLL Architecture Based on Phase Prediction

We propose a new generalized all-digital phase-locked loop (ADPLL) architecture that allows to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC). In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. The proposed architecture is verified through behavioral simulations. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation.