An Introduction to High-Level Synthesis

被引：187
作者：
Coussy, Philippe [1 ]
Meredith, Michael
Gajski, Daniel D. [2 ]
Takach, Andres
机构：
[1] Univ Bretagne Sud, Lab STICC, Ctr Rech, F-56321 Lorient, France
[2] Univ Calif Irvine, Ctr Embedded Comp Systems, Irvine, CA USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2009年 / 26卷 / 04期
关键词：
Architectures; Custom processors; Design and test; Hardware; Hardware synthesis and verification; High-level synthesis; Memory management; Multiplexing; Registers; Resource management; RTL abstraction; Software;
D O I：
10.1109/MDT.2009.69
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Editor's note: High-level synthesis raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements. This article gives an overview of state-of-the-art HLS techniques and tools. © 2009 IEEE.
引用
收藏
页码：8 / 17
页数：10
相关论文
共 25 条
[1]  
[Anonymous], 2008, HIGH LEVEL SYNTHESIS
[2]  
AUGE I, 2008, HIGH LEVEL SYNTHESIS, P171
[3]  
Bailey B., 2007, ESL Design and Verification: A Prescription for Electronic System Level Methodology
[4]  
Chang H., 1999, SURVIVING SOC REVOLU
[5]  
Chen Deming., 2006, FPGA design automation: A survey
[6]  
Elliot J.P., 1999, Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
[7]  
Gajski D.D., 2000, SpecC: Specification Language and Methodology
[8]  
Gajski D.D., 1992, High-level synthesis: introduction to chip and system design
[9]  
GEURTS W, 1996, ACCELERATOR DATA PAT
[10]   AUTOMATIC EXTRACTION OF FUNCTIONAL PARALLELISM FROM ORDINARY PROGRAMS [J].
GIRKAR, M ;
POLYCHRONOPOULOS, CD .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1992, 3 (02) :166-178
123