Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

被引：0

作者：

Gebreyohannes, Fikre Tsigabu ^{[1
]}

Louerat, Marie-Minerve ^{[1
]}

Aboushady, Hassan ^{[1
]}

机构：

[1] Sorbonne Univ, CNRS, LIP6, F-75005 Paris, France

来源：

2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2019年

关键词：

multi-stage amplifiers; Feed-forward compensation; sigma-delta modulators; bandpass; continuous-time; BANDWIDTH;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a 4th-order multi-stage, multi-path, feed-forward-compensated operational amplifier in 65 nm CMOS technology. It is designed to meet the requirements of a continuous-time bandpass Sigma Delta modulator with multi-GHz sampling frequency. The designed amplifier is modular with each stage implemented based on a unit differential amplifier block and it meets its targets with smart placement of poles and zeros. The amplifier is simulated under the loading condition of a single-amplifier resonator which is in turn part of a 6th- order Sigma Delta modulator. The unloaded amplifier reaches a unity-gain-frequency of 38.29 GHz and a DC gain of 58 dB. With a parallel load of 440 fF and 300 Omega, representing the maximum load, the op-amp, including common-mode and biasing circuits, consumes a total of 18.98 mA from a supply voltage of 1.2 V. It is unconditionally stable with a phase margin of 54 degrees and has gains of 35 dB and 23 dB at 1 GHz and 2 GHz respectively.

引用

页数：5

共 8 条

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