Design Study of the Bump on Flexible Lead by FEA for Wafer Level Packaging

被引：0
|
作者：
Eidner, I. [1 ]
Wunderle, B. [2 ]
Pan, K. L. [3 ]
Wolf, M. J. [2 ]
Ehrmann, O. [1 ]
Reichl, H. [1 ]
机构：
[1] Tech Univ Berlin, Gustav Meyer Allee 17A,TIB 4-2-1, D-13355 Berlin, Germany
[2] Fraunhofer Inst Reliabil & Microintegrat, D-13355 Berlin, Germany
[3] Guilin Univ Elect Technol, Guilin 541004, Peoples R China
来源：
EUROSIME 2009: THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS | 2009年
关键词：
RELIABILITY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The Bump on Flexible Lead (BoFL) is a chip-to-substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer (RDL) embedded in a polyimide-bridge which is located over an air gap. Since the stress due to CTE mismatch is then accommodated within the flexible lead, the risk of solder fatigue decreases. The new failure risks are mainly related to fatigue of the copper RDL. Therefore a design study of the flexible lead by finite element analysis (FEA) was performed. The parameters investigated were the polyimide thickness, the thickness of the copper RDL and the shape of the copper RDL. The results obtained from the simulation study are useful to form design guidelines for enhanced board level reliability of the BoFL-WLP.
引用
收藏
页码：348 / +
页数：3
相关论文
共 50 条
  • [31] Shock Performance Study of Solder Joints in Wafer Level Packages
    Ranouta, Amarinder Singh
    Fan, Xuejun
    Han, Qiang
    2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009), 2009, : 1185 - +
  • [32] Low-Temperature Wafer-Level Bonding with Cu-Sn-In Solid Liquid Interdiffusion for Microsystem Packaging
    Golim, Obert
    Vuorinen, Vesa
    Wernicke, Tobias
    Pawlak, Marta
    Paulasto-Krockel, Mervi
    MICROELECTRONIC ENGINEERING, 2024, 286
  • [33] Study of the Board Level Reliability Performance of a Large 0.3 mm Pitch Wafer Level Package
    Waidhas, Bernd
    Proschwitz, Jan
    Pietryga, Christoph
    Wagner, Thomas
    Keser, Beth
    2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2019, : 1159 - 1164
  • [34] Design and reliability analysis of wafer level package with bubble-like buffer layer
    Lee, CC
    Chiang, KN
    ADVANCES IN ELECTRONIC PACKAGING 2003, VOL 2, 2003, : 813 - 818
  • [35] Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments
    Rzepka, S
    Höfer, E
    Simon, E
    Meusel, E
    Reichl, H
    IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2002, 25 (02): : 127 - 137
  • [36] Design and analysis of NCP packaging process for fine-pitch flexible printed circuit board
    Shim J.H.
    Cha D.H.
    Journal of Institute of Control, Robotics and Systems, 2010, 16 (02) : 172 - 176
  • [37] Utilizing Co as a contact metallization for wafer-level Cu-Sn-In SLID bonding used in MEMS and MOEMS packaging
    Emadi, Fahimeh
    Vuorinen, Vesa
    Paulasto-Krockel, Mervi
    2022 IEEE 9TH ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE, ESTC, 2022, : 359 - 363
  • [38] An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging
    Chen, K. M.
    Wu, C. Y.
    Wang, C. H.
    Cheng, H. C.
    Huang, N. C.
    JOURNAL OF ELECTRONIC MATERIALS, 2014, 43 (11) : 4229 - 4240
  • [39] High-toughness (111) nano-twinned copper lines for fan-out wafer-level packaging
    Li, Yu-Jin
    Hsu, Wei-Yu
    Lin, Benson
    Chang, ChiaCheng
    Chen, Chih
    2019 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP 2019), 2019, : 251 - 254
  • [40] EFFECT OF DESIGN PARAMETERS ON DROP TEST PERFORMANCE OF WAFER LEVEL CHIP SCALE PACKAGES (WLCSP)
    Tumne, Pushkraj
    Venkatadri, Vikram
    Kudtarkar, Santosh
    Delaus, Michael
    Santos, Daryl
    Havens, Ross
    Srihari, Krishnaswami
    PROCEEDINGS OF THE ASME PACIFIC RIM TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC SYSTEMS, MEMS AND NEMS 2011, VOL 1, 2012, : 713 - +
12345